(a) Field of the Invention
The present invention relates to a field effect transistor having comb-shaped electrode assemblies.
(b) Description of the Related Art
Field effect transistors (FET) having comb-shaped electrode assemblies are generally used in a compound semiconductor device. FIG. 1 shows a conventional FET of this type. The FET has a plurality of source electrodes 17, a plurality of drain electrodes 8 and a plurality of gate electrodes 21, all are aligned on an active stripe region 12 in a horizontal direction as viewed in FIG. 1. The plurality of source electrodes 17, plurality of drain electrodes 18 and plurality of gate electrodes 21 are respectively connected in parallel to respective bonding pads 27, 28 and 30 by bus bars 25, 26 and 21A to thereby form comb-shaped electrode assemblies, respectively.
FIGS. 2A to 2G, FIGS. 3A to 3G and FIGS. 4 to 7 show a process for manufacturing the FET of FIG. 1, in which FIGS. 2A to 2G are cross-sections taken along line A-A' while FIGS. 3A to 3G are cross-sections taken along line B-B' in consecutive steps of the process, and in which FIGS. 4 to 7 are plan views of the FET of FIG. 1 in the consecutive steps. Detailed structure of the conventional FET of FIG. 1 will be described through description of the process thereof with reference to those drawings.
A stripe n-GaAs region 12 is formed on a selected portion of a semi-insulating GaAs substrate 11, following which a first insulator layer 13 made of SiO.sub.2, for example, is deposited on the entire surface of the substrate 11 including the surface of the stripe n-GaAs region 12. The first insulator layer 13 is then selectively removed by an etching step using a photoresist pattern 14 as a mask, to thereby form openings 15 for receiving therein source and drain electrodes. FIGS. 2A and 3A show this stage of the FET.
A first layer metal laminate 16, 17 and 18 including consecutively, as viewed from the bottom, AuGe, Ni, and Au (AuGe/Ni/Au) films is deposited by evaporation onto the entire surface including the surfaces of the photoresist pattern 14 and the stripe n-GaAs region 12 in the opening 15, as shown in FIGS. 2B and 3B. The first layer metal laminate 16 on the photoresist pattern 14 is then removed by a lift-off method through removing the photoresist pattern 14, as shown in FIGS. 2C and 3C. Thereafter, a thermal treatment of the first layer metal laminate 17 and 18 on the stripe n-GaAs layer 12 is effected to form an alloy, thereby obtaining the source and drain electrodes 17 and 18 which contact the active stripe n-GaAs region 12 by way of ohmic contact. The metal patterns 17 and 18 as obtained by those steps are shown in FIG. 4.
A second insulator layer 19 made of SiO.sub.2 is deposited on the entire surface, and the first and second insulator layers 13 and 19 are selectively etched to form openings 20 therein (FIGS. 2D, 3D and 5). Thereafter, a second layer metal laminate 21 including consecutively, as viewed from the bottom, WSi and Au (WSi/Au) films is deposited by sputtering and patterned to form a comb-shaped gate structure including a plurality of gate electrodes 21 formed on the stripe n-GaAs region 12 and a gate bus bar 21A formed on the semi-insulating substrate 11, as shown in FIGS. 2E, 3E and 6. The gate electrodes 21 contact the n-GaAs layer 12 by way of a Schottky contact.
Subsequently, a third insulator layer 23 made of SiO.sub.2 is formed on the entire surface including the surfaces of the gate structure 21 and 21A and the second insulator layer 19. The second and third insulator layers 19 and 23 are then selectively and consecutively etched to form therein openings 24 for exposing the source electrodes 17 and drain electrodes 18 and an opening 29 for gate bus bar (FIGS. 2F, 3F and 7). Thereafter, a third layer metal laminate made of WSi/Au films is deposited by sputtering onto the entire surface, then selectively etched to form a gate pad 30 on the gate bus bar 21A, a comb-shaped source bus bar 25 having a pair of source pads 27, and a comb-shaped drain bus bar 26 having a drain pad 28, as shown in FIGS. 1, 2G and 3G.
The conventional compound FET as described heretofore has a three-layer metal structure including the first layer implementing the source electrodes 17 and drain electrodes 18, the second layer implementing the gate structure 21 and 21A, and the third layer implementing the source and drain bus bars 25 and 27 connecting the source electrodes and drain electrodes together, respectively, and the gate pad 30. The three-layer metal structure of the FET requires a large number (six) of photolithographic steps for metal and insulator layers, thereby raising the fabrication costs of the FET.